Xilinx Virtex-5 RocketIO GTP

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 21
UG196 (v1.3) May 25, 2007
Overview
R
Figure 1-1: GTP_DUAL Inside the Virtex-5 LX110T FPGA
Virtex-5 LX110T
Config
and
Clock
Ethernet
MAC
Ethernet
MAC
GTP_
DUAL
X0_Y7
GTP_
DUAL
X0_Y6
GTP_
DUAL
X0_Y5
GTP_
DUAL
X0_Y4
GTP_
DUAL
X0_Y3
GTP_
DUAL
X0_Y2
GTP_
DUAL
X0_Y1
GTP_
DUAL
X0_Y0
CMT
CMT
CMT
CMT
CMT
CMT
I/O
Column
I/O
Column
CRC
Blocks
CRC
Blocks
CRC
Blocks
CRC
Blocks
CRC
Blocks
CRC
Blocks
CRC
Blocks
CRC
Blocks
UG196_c1_01_051507
PCI
Express
Notes:
1. This figure does NOT illustrate exact size, location or scale of the functional blocks to each other. It does show the correct
number of available resources.