Xilinx Virtex-5 RocketIO GTP User Manual

294 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Appendix D: DRP Address Map of the GTP_DUAL Tile
R
SATA_MIN_BURST_0
3f<10>
3f<11>
3f<12> 3f<13> 3f<14> 3f<15>
SATA_MIN_BURST_1
10<5> 10<4> 10<3> 10<2> 10<1> 10<0>
SATA_MIN_INIT_0
3f<4> 3f<5> 3f<6> 3f<7> 3f<8> 3f<9>
SATA_MIN_INIT_1
10<11>
10<10>
10<9> 10<8> 10<7> 10<6>
SATA_MIN_WAKE_0
3e<14> 3e<15>
3f<0> 3f<1> 3f<2> 3f<3>
SATA_MIN_WAKE_1
11<1> 11<0>
10<15> 10<14> 10<13> 10<12>
TERMINATION_CTRL
29<5> 29<4> 29<3> 29<2> 29<1>
TERMINATION_OVRD
29<6>
TRANS_TIME_FROM_P2_0
3d<13> 3d<14> 3d<15>
3e<0> 3e<1> 3e<2> 3e<3> 3e<4> 3e<5> 3e<6> 3e<7> 3e<8> 3e<9>
3e<10>
3e<11>
3e<12>
TRANS_TIME_FROM_P2_1
12<2> 12<1> 12<0>
11<15> 11<14> 11<13> 11<12>
11<11>
11<10>
11<9> 11<8> 11<7> 11<6> 11<5> 11<4> 11<3>
TRANS_TIME_NON_P2_0
3c<13> 3c<14> 3c<15>
3d<0> 3d<1> 3d<2> 3d<3> 3d<4> 3d<5> 3d<6> 3d<7> 3d<8> 3d<9>
3d<10>
3d<11>
3d<12>
TRANS_TIME_NON_P2_1
13<2> 13<1> 13<0>
12<15> 12<14> 12<13> 12<12>
12<11>
12<10>
12<9> 12<8> 12<7> 12<6> 12<5> 12<4> 12<3>
Table D-2: DRP Address by Attribute (Continued)
Attribute
Bit
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English