Xilinx Zynq UltraScale+ ZCU216 - Page 8

• PL DDR4 C1 I/F 2 GB 32-bit Component (4x8-bit)
• PS GTR (Bank505) assignment
○ USB3 (1 GTR)
○ SATA w/M2 Connector (1 GTR)
○ 2 GTR not used
• PL GTY assignment (4 Quads, 16 total GTY)
○ zSFP+ (4 GTY, 2 on quad GTY128 and 2 on quad GTY129)
○ 8A34001 (1 GTY, quad GTY128)
○ Carlisle CoreHC2 J128 (1 GTY, quad GTY129)
○ FMCP HSCP DP (4 GTY, bank GTY130)
○ FMCP HSCP DP (4 GTY, bank GTY131)
○ 1 GTY not used (quad GTY128)
○ 1 GTY not used (quad GTY129)
• PL FMCP HSCP (FMC+) Connecvity - Full LA[00:33] Bus
• PS MIO Connecvity
○ PS MIO[0:5, 7:12]: Dual QSPI
○ PS MIO[13]: PS_GPIO2
○ PS MIO[14:17]: 2 channels of I2C
○ PS MIO[18:19]: UART0 (1 of 3 FT4232 UART channels)
○ PS MIO[22:23]: PS_PB, PS_LED I/F
○ PS MIO[26]: PMU
○ PS MIO[32:37]: PMU_GPO[0:5]
○ PS MIO[38]: PS_GPIO1
○ PS MIO[40:42, 45:51]: SD I/F
○ PS MIO[52:63]: USB3.0
○ PS MIO[64:77]: Ethernet RGMII
• PL I/O Connecons:
○ PL User DIP switch (8-posion)
○ PL User pushbuons (5, Geographic N, S, E, W, C)
Chapter 1: Introduction
UG1390 (v1.1) July 10, 2020 www.xilinx.com
ZCU216 Board User Guide 8
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