ABB REL650 - Page 134

of figure 55 (internal input signal ZOUTL1, ZINL1, AND-gates and tP-timers) are
duplicated for phase L2 and L3. All tP1 and tP2 timers in the figure have the same
settings.
IEC05000113-2-en.vsd
AND
ZINL1
AND
DET-L1
OR
AND
AND
ZOUTL1
-loop
ZOUTL2
ZOUTL3
OR
detected
OR
-loop
0-tP1
0
0-tP2
0
0
0-tW
IEC05000113 V2 EN-US
Figure 55: Detection of power swing in phase L1
IEC01000057-2-en.vsd
DET-L1
DET-L2
DET-L3
DET1of3 - int.
DET2of3 - int.
&
&
&
>1
>
1
IEC01000057-TIFF V2 EN-US
Figure 56: Detection of power swing for 1-of-3 and 2-of-3 operating mode
Section 6 1MRK 506 382-UEN A
Impedance protection
128 Line distance protection REL650 2.2 IEC
Technical manual