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3. BR93L46RF (IC35)
Vcc
NC
NC
GND
CS
SK
DI
DO
Pin Name I/O Function
Vcc - Power Supply
GND - GND
CS INPUT Chip Selct
SK INPUT Serial Clock Input
DI INP Start bit,Cord,Address,Serial data
DO OUTPUT Serial data input, READY/BUSY status
4. HD74LV00 (IC29)
1
2
3
4
5
7
6
1A
1B
1Y
2A
2B
GND
2Y
VCC
4B
4A
4Y
3B
3Y
3A
14
13
12
11
10
8
9
5. HD74LV74 (IC25)
TG
C
C
TG
C
TG
C
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
logic diagram, each flip-flop (positive logic)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
HLXXLH
LLXXH
Ü
H
Ü
HH HHL
HH LLH
H H L XQ
0
Q
0
Ü
This configuration is nonstable; that is, it does not
persist when PRE
or CLR returns to its inactive
(high) level.