Tbe read circuitry
I:lt:1Ys
iu
a reset state for the first sevell or eight hOrlzolltal video
SC:1l1
lines. Following the reset interval, the circuit allows a charge
to
begin building up on a
timing capacitor whose charge rate will be controlled by the position of the external con-
troller resistance. For each horizontal scan line thereafter, the circuit compares the
charge on the timing capacitor
to
a preset value.
If
the charge
is
below
that
value, one
count is added
to
the counter for
that
POT. If
it
is
above
that
value, the counter value
will be held
at
the stopped value until the next POTGO
is
issued.
Effects
of
Different
Resistance
on
Charging
Rate
You normally issue POTGO
at
the beginning of a video screen, then read the values in
the
POT
registers during the next vertical blanking period, just before issuing POTGO
again. (Again note
that
this
is
an automatic feature of the operating system.)
Nothing in the system prevents the counters from overflowing (wrapping past a count of
255). However, the system
is
designed
to
insure
that
the counter cannot overflow within
the span of a single screen. This allows you
to
know for certain whether an overflow
is
indicated by the controller.
Although there are
262
or
263
possible horizontal scan lines on a single NTSC video
screen, each of the
POT
counters
is
eight bits wide, which allows a maximum of
255
in
any counter. This is why the control circuitry is delayed seven or eight horizontal scan
lines-to
limit the maximum
POT
count value
to
255.
Proportional
Controller
Registers
The following registers are used for the proportional controllers:
POTODAT - port 0
data
(vertical/horizontal)
POT1DAT - port 1
data
(vertical/horizontal)
Bit positions:
Bits
15-8
POTOY value or POT1 Y value
Bits
7-0
POTOX value or POT1X value
All counts are reset
to
zero when POTGO is written. Counts- are normally read one
screen after the scan circuitry is enabled.
Interface Hardware
223
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