Commodore Amiga - Page 262

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COPJMPI
088
S
A
Copper restart at first location
COPJMP2
OSA
S A Copper restart at second location
0)
These addresses are strobe addresses.
When written
to, they cause the Copper to jwrp indirect using
the address contained in the first or second
location registers described below. The Copper
itself can write to these addresses, causing its
own jwrp indirect.
COPlLCH
080 W A Copper first location register
(high 3 bits)
COPlLCL 082 W A Copper first location register
(low 15 bits)
COP2LCH
084 W A
Copper second location register
(high 3 bits)
COP2LCL 086 W A
Copper second location register
(low 15 bits)
These registers contain the jwrp addresses
described above.
COPINS
OBC
W A Copper instruction fetch identi fy
This is a dummy address that is generated by the
Copper whenever it is loading instructions into
its own instruction register. This actually occurs
every Copper cycle except for the second (IR2)
cycle of the MOVE instruction. The three types
of instructions are shown below.
MOVE Move immediate to destination.
WAIT
Wait until beam counter is equal to, or
greater than. (keeps Copper off of bus
until beam position has been reached) •
SKIP
Skip if beam counter is equal to or
greater than (skips following MOVE
instruction unless beam position has
been reached) •
MOVE WAIT UNTIL
SKIP IF
--------
-----------
------------
BIT#
IRI IR2
IRI IR2 IRI
IR2
15
X RD1S VP7
BFD *
VP7
BFD *
14 X
RD14
VP6 VE6 VP6
VE6
13 X RD13
VPS
VES
VPS VES
12 X RD12
VP4
VE4
VP4 VE4
11
X
RD11 VP3
VE3
VP3 VE3
10 X RDIO
VP2
VE2
VP2 VE2
09 X RD09 VPl VEl VPl
VEl
08
DAB RD08 VPO VEO VPO
VEO
07 DA7 RD07 IIP8 HE8 lIPS
HE8
06 DA6
RD06 IIP7
HE7
IIP7 HE7
05 DA5 RDOS
IIP6
HE6
IIP6 HE6
04 DA4 RD04
lIPS
HES
lIPS HES
03 DA3 RD03
IIP4
HE4 IIP4
HE4
02 DA2 RD02
IIP3
HE3
IIP3
HE3
01 DA1
RDOI
IIP2 HE2
IIP2 HE2
00
0
RDOO
1
0
1
1
DIWSTRT
DIWSTOP
IR1=First instruction register
IR2=Second instruction register
DA =Destination address for MOVE instruction.
Fetched during IRI time, used during IR2 time
on RGo\ bus.
RD =RAM data moved by MOVE instruction at IR2 time
directly from RAM to the address given by the
DA field.
VP =Vertical beam position comparison bit.
lIP =Horizontal beam position comparison bit.
VE =Enable comparison (mask bit) •
HE =Enable comparison (mask bit) •
* NOTE BFD=Blitter finished disable. When this bit
is true, the Blitter Finished flag will
have no effect on the Copper. When this
bit is zero, the Blitter Finished flag
must be true (in addition to the rest of
the bit comparisons) before the Copper
can exit from its wait state or skip
over an instruction. Note that the V7
comparison cannot be masked.
The Copper is basically a two-cycle machine that
requests the bus only during odd memory cycles
(4 memory cycles per instruction). This prevents
collisions with display, audio, disk, refresh, and
sprites, all of which use only even cycles. It
therefore needs (and has) priority over only the
blitter and microprocessor.
There are only three types of instructions:
MOVE immediate, WAIT until, and SKIP if. All
instructions (except for WAIT) require two bus
cycles (and two instruction words). Since only
the odd bus cycles are requested, four memory
cycle times are required per instruction
(memory cycles are 280 ns.)
There are two indirect jwrp registers, COPlLC and
COP2LC. 1'hese are IS-bit pointer registers whose
contents are used to modify the program counter for
initialization or jwrps. They are transferred to
the program counter whenever strobe addresses
COPJMPI or COPJMP2 are written. In addition,
COPlLC is automatically used at the beginning of
each vertical blank time.
It is important that one of the jwrp registers be
initialized and its jwrp strobe address hit after
power-up but before Copper DMA is initialized.
This insures a determined startup address and state.
OSE W A
090 W A
Display window start (upper left
vertical-horizontal position)
Display window stop (lower right
vertical-horizontal position)