Commodore Amiga - Page 264

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DSKBY'l'R
OlA
R
P
Disk data byte and status read
'!his register is the disk-microprocessor data
00
buffer. Data from the disk (in read mode) is
loaded into this register one byte at a time, and
bit 15 (DSKSYT) is set true.
BITt
---------
--------------------------------
15 DSKBYT
Disk byte ready (reset on read)
14 SMAON
Mirror of bit 15 (DMAEN) in DSKLEN,
ANDed with Bit09 (DMAEN) in DMACON
13
DISKWRlTE
Mirror of bit 14 (WRITE) in DSKLEN
12
t«>RDEQUAL
'!his bit true only while the
DSKSYNC register equals the data
from disk.
11-08
X
Not
used
07-00 DATA
Disk byte data
DSKSYNC 07E
W
P
Disk sync register, holds the match
code for disk read synchronization.
See ADKCON bit 10.
INTREQ 09C
W P
Interrupt request bits (clear or set)
INTREQR OlE
R P Interrupt request bits (read)
This register contains interrupt request bits (or
flags). These bits may be polled by the processor;
if enabled by the bits listed in the next register,
they may cause processor interrupts. Both a set and
clear operation are required to load arbitrary data
into this register.
These status bits are not
automatically reset when the interrupt is serviced,
and IIJlst be reset when desired by writing to this
address.
'!he bit assignments are identical to the
enable register below.
INTENA 09A
W
P
Interrupt enable bits (clear or set bits)
INTENAR 01C
R P Interrupt enable bits (read)
This register contains interrupt enable bits. '!he bit
assignment for both the request and enable registers
is given below.
BITt
FUNCT
LEVEL DESCRIPTION
------ ----- ----------------------------------
15
SET/CLR
Set/clear control bit. Determines if
bits written with a 1 get set or
cleared. Bits written with a zero
are always unchanged.
14 INTEN
Master interrupt (enable only,
no request)
13 EXTER 6
External interrupt
12
DSKSYN
5
Disk sync register (DSKSYNC)
matches disk data
11 RBF
5
Serial port receive buffer full
10
AUD3 4
Audio
channel 3 block finished
09 AUD2 4
Audio
channel 2 block finished
08
AUDl 4
Audio
channel 1 block finished
07
AUDO 4
Audio
channel ° block finished
JOYODAT
OOA
JOYlDAT
OOC
06 BLIT
3
Blitter finished
05 VERTB
3 Start of vertical blank
04
COPER 3 Copper
03 PORTS
2 I/O ports and timers
02
SOE"T 1
Reserved for software-initiated
interrupt
01 DSKBLK
1
Disk block finished
00 TBE 1 Serial port transmit buffer eapty
R D Joystick-mouse 0 data (left vertical,
horizontal)
R D Joystick-mouse 1 data (right vertical,
horizontal)
These addresses each read a pair of 8-bit mouse
counters. O=left controller pair, l=right
controller pair (four counters total). '!he bit
usage for both left and right addresses is shown
below. Each counter is clocked by signals from
two
controller pins. Bits 1 and ° of each counter
may be read to determine the state of these two
clock pins. '!his allows these pins to double as
joystick switch inputs.
Mouse counter usage:
(pins 1.3=Yclock, pins 2.4=Xclock)
BIT#
15.14.13.12,11.10.09,08 07.06,05.04,03.02.01.00
OOAT Y7 Y6 Y5 Y4 Y3 Y2 Yl YO X7 X6 XS X4 X3 X2 Xl XO
lDAT Y7 Y6 Y5 Y4 Y3 Y2 Yl YO X7 X6 XS X4 X3 X2 Xl XO
The following table shows the mouse/joystick
connector pin usage. '!he pins (and their functions)
are sarrpled (lIJlltiplexed) into the DENISE chip
during the clock times shown in the table.
'!his table is for reference only and should
not be needed by the programner. (Note that the
joystick functions are all "active low" at the
connector pins.)
Sarrpled by DENISE
Conn
Joystick Mouse
-----------------
Pin
Function Function
Pin Name
Clock
--------
-------.
----
-----
Ll FORW* Y
38
MOV at CCK
L3
LEFT* YQ
38
MOV at CCK*
L2
BACK*
X
9
MOH at CCK
L4 RIGH*
XQ
9 MOH at CCK*
Rl FORW* Y
39
MIV at CCK
R3
LEFT*
YQ 39
MlV at CCK*
R2
BACK* X
8
M1H at CCK
R4
RIGH*
XQ
8
M1H at CCK*
After being sarrpled, these connector pin signals
are used in quadrature to clock the mouse counters.
'!he LEFT and RIGHT joystick functions (active high)
are directly available on the Yl and Xl bits of
each counter. In order to recreate the FORWARD
and BACK joystick functions, however, it is