DDC Total-AceXtreme MIL-STD-1553 User Manual

Total-AceXtreme
®
Ultra-Small, Ultra-Low Power
MIL-STD-1553 Single Package Solution
Data Sheet
© 2011 Data Device Corporation. All trademarks are the property of their respective owners.
Model: BU-67301B
For more information: www.ddc-web.com/BU-67301B
• Small, Fully Integrated 1553 Terminal with
Transformers Inside:
- 16 x 16 x 4.7 mm (0.63 x 0.63 x 0.185 in.)
- Protocol, RAM, Transceivers and Transformers in a
Single Package
- 324 Ball JEDEC Design Guide 4.5 Standard Size
Fine Pitch Ball Grid Array with 0.8 mm Ball Pitch
• Ultra Low Transceiver Power
• Comprehensive Built-in Self Test
• Versatile User Selectable High-Speed Backend for
PCI or CPU Interface
- Access Time as low as 12.5ns
- DMA Engine with 264MB/sec Burst Transfer Rate
• 1 Dual Redundant MIL-STD-1553 Channel
- BC or Multi-RT with Concurrent Bus Monitor
- Supports MIL-STD-1553 A/B and MIL-STD-1760
- 2 Mb (64K x 36) RAM
- Tx Inhibit Ball for MT Only Applications
- BC Disable Ball for RT Only Applications
- 48-bit/100ns Time Stamp
- IRIG-106 Chapter 10 MT Support
• Supports JTAG Boundary Scan
• IRIG-B Input
• 8 Digital Discrete I/O
• Hardware/Software Development Kit with PCI
Evaluation Board and Reference Design Artifacts
Features
World's smallest, ultra low power, fully integrated MIL-STD-1553 BGA package, complete with 1553 protocol,
2 Mb (64K x 36) RAM, transceivers, and isolation transformers inside a single package — saves board space and
simplifies 1553 design and layout. Available with development kit to ease integration.

DDC Total-AceXtreme MIL-STD-1553 Specifications

General

Brand	DDC
Model	Total-AceXtreme MIL-STD-1553
Category	Transceiver
Language	English

Summary

Product Features

Product Overview and Specifications

Product Feature Highlights

Summarizes key features including integration, low power, and configurable interfaces.

Technical Specifications and Ratings

Details electrical and physical characteristics, including supply voltages and tolerances.

MIL-STD-1553 Modes and Architecture

Bus Controller (BC) Mode Operation

Explains the Bus Controller architecture, command interpreter, and queues.

Built-In Test (BIT) and Diagnostics

On-line and Off-line Self-Test Functions

Details continuous loopback, RT protocol, and Bus A to Bus B loopback tests.

JTAG Boundary Scan for Board Testing

Describes the IEEE 1149.1 compliant JTAG port for board-level verification.

Host Interface Options and Signals

Host Interface Configuration Settings

Parallel CPU Interface Modes

Explains Asynchronous vs. Synchronous, 16/32-bit, and multiplexed modes.

Asynchronous CPU Interface Operation

Synchronous CPU Interface Operation

PCI Interface Compliance and Features

Lists features and characteristics of the PCI 2.3 compliant interface.

Power Supply Requirements and Sequencing

Recommended Decoupling Capacitors

Lists recommended decoupling capacitor values for various power supply pins.

Power-Up Initialization Sequence

Details the required power-up sequence and timing for proper initialization.

MIL-STD-1553 Transceiver Options

Using Internal Transceivers and Transformers

External Fiber Optic Transceiver Interface

Thermal Management Considerations

Register and Memory Addressing

Memory Address Space Access

Register Address Space Access

Signal Descriptions and Pinout

Signal Descriptions by Functional Group

Host Interface Signal Details