TOTAL- ACEXTREME® SIGNALS
Data Device Corporation DS-BU-67301B-G
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11.3 Pinout Table
Table 26. Signal Pinout by Ball Location
BALL Signal Name BALL Signal Name BALL Signal Name
A1 NC G1 PCI_AD(19)/CPU_DATA(19) N1 PCI_AD(12)/CPU_DATA(12)
A2 NC G2 PERR#/CPU_ADDR(11) N2 PCI_AD(08)/CPU_DATA(08)
A3 NC G3 PCI_AD(18)/CPU_DATA(18) N3 PCI_AD(07)/CPU_DATA(07)
A4
PCI_AD(30)/CPU_DATA(
30) G4 GND_LOGIC N4 PCI_AD(06)/CPU_DATA(06)
A5
PCI_AD(31)/CPU_DATA(
31) G5 GND_LOGIC N5 +3.3V_XCVR
A6
PCI_GNT#/CPU_ADDR(1
3) G6 GND_LOGIC N6 +3.3V_XCVR
A7 JTAG_TCK G7 GND_LOGIC N7 +3.3V_XCVR
A8 CLOCK_IN G8 GND_LOGIC N8 +3.3V_XCVR
A9 INTA# G9 GND_LOGIC N9 +3.3V_XCVR
A10 JTAG_TMS G10 RTAD2 N10 NC
A11 GND_LOGIC G11 RT_AD_LAT N11 NC
A12 GND_LOGIC G12 RTAD3 N12 NC
A13 PLL_LOCKED G13 RTAD1 N13 TAG_ENABLE
A14 GND_LOGIC G14 RTAD0 N14 IRIG_DIG_IN
A15 GND_LOGIC G15 NC N15 NC
A16 NC G16 NC N16 NC
A17 NC G17 CHA_1553 N17 CHB_1553 (I/O)
A18 NC G18 CHA_1553 N18 CHB_1553 (I/O)
B1 NC H1 PCI_AD(16)/CPU_DATA(16) P1 CPU_nSTOP
B2 NC H2 STOP#/CPU_ADDR(08) P2 nINT
B3
PCI_AD(27)/CPU_DATA(
27) H3 FRAME#/CPU_ADDR(05) P3 CPU_WORD_EN(0)
B4
PCI_AD(28)/CPU_DATA(
28) H4 +3.3V_LOGIC P4 CPU_WORD_EN(1)
B5
PCI_AD(29)/CPU_DATA(
29) H5 +3.3V_LOGIC P5 GND_XCVR
B6 RST#/nMSTCLR H6 +3.3V_LOGIC P6 GND_XCVR
B7 REQ#/CPU_ADDR(12) H7 +3.3V_LOGIC P7 GND_XCVR
B8 JTAG_TDO H8 +3.3V_LOGIC P8 GND_XCVR
B9 JTAG_nTRST H9 +3.3V_LOGIC P9 GND_XCVR
B10 JTAG_TDI H10 TXINH_OUT_A P10 NC
B11 GND_LOGIC H11 TXINH_IN_A P11 GND_XCVR
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