DDC Total-AceXtreme MIL-STD-1553 - Figure 42. Synchronous, Non-Multiplexed Address - 16-Bit Random Burst Write Transfer Timing

HOST INTERFACE
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CPU_DATA
nDATA_RDY
HOST_CLK
CPU_WORD_EN[
1
:0
]
RD_
nWR
MEM_
nREG
CPU_ADDR
nDATA_STRB
nSELECT
CPU_nLAST
MSW_nLSW
CPU_nSTOP
tAHtAS
tAH
tRDD
tLS
tCLK
tAS
tAS
tDHtDS
tSH
tCS
tSS
tRDD
tAH
tAH
tCH
Data
Data
Data
Data
Data
Data
Data
Data
Data
tAH
Address
Address
Address
Address
Address
tAS
tDH
Data
tAH
tLH
tLS
tAS
tSHC
tWait
Figure 42. Synchronous, Non-Multiplexed Address - 16-bit Random Burst Write
Transfer Timing
Figure 42 Notes:
1. For a random burst write transfer, both nDATA_STRB and nSELECT must be
asserted low through the entire time of the transfer. The nDATA_RDY output
is initially asserted low on the clock cycle prior to the cycle in which the Total-
AceXtreme® reads the first 16-bit data word from the data bus. CPU_nLAST
must be asserted high until the last 16-bit word is to be written. On the rising
clock edge following CPU_nLAST asserting low, the Total-AceXtreme reads
the last 16-bit word from the data bus, and nDATA_RDY is de-asserted (high).
At this time (or later) nDATA_STRB and nSELECT must be de-asserted high,
completing the burst write transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full
transfer cycle.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.