MIL- STD- 1553 MODES AND ARCHITECTURE
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images, discretes, UARTs, IEEE 1394, parallel, IRIG time, video, and voice. In
addition, Chapter 106 provides standardization of time bases.
For MIL-STD-1553, IRIG 106 Chapter 10 defines packets that can encapsulate one
of more 1553 messages. Within these packets, all messages are tagged with either a
48-bit relative or 64-bit absolute time stamp. For each message, there is also a block
status word, which includes indications of bus channel and message validity, and
identifies specific errors. The 1553 format also defines indications of response time,
plus storage of all 1553 Command, Status, and Data Words, in the order received.
For supporting IRIG 106 Chapter 10, the Total-AceXtreme® includes DMA
capability, which operates in conjunction with the PCI Initiator interface to transfer
monitored data from the 1553 monitor to PCI host space.
Figure 5. Monitor Block Diagram - Advanced Data Handler (ADH)
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