HOST INTERFACE
Data Device Corporation DS-BU-67301B-G
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Figure 26. Synchronous, Non-Multiplexed Address 16-bit - Single-Word Memory Read
Timing
Figure 26 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle, and
de-asserted high at the end of the transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full
transfer cycle.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP will not be
asserted for memory accesses, and will remain high.
MSW_nLSW
MEM_nREG
RD_nWR
CPU_WORD_EN[1:0]
nDATA_RDY
nSELECT
CPU_ADDR
nDATA_STRB
CPU_DATA
HOST_CLK
CPU_nSTOP
tDD
tCLK
Data A
tWait
tWait
Data B
tRDD
tRDD
tRDD
tOHZ
tOH
tOHZ
tOH
tDD
tSS
tCS
tSS
tCS
tCH
tCH
tSHtSH
tRDD
Address
tAS
tAS
tAS
tAS
tAS
tAH
tAH
tAH
tAH
tAH
tAS
tSHC
CPU_nLAST
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