DDC Total-AceXtreme MIL-STD-1553 - Figure 38. Synchronous, Non-Multiplexed Address - 32-Bit Sequential Burst Write Transfer Timing

HOST INTERFACE
Data Device Corporation DS-BU-67301B-G
www.ddc-web.com
1/14
78
Figure 38. Synchronous, Non-Multiplexed Address - 32-bit Sequential Burst Write
Transfer Timing
Figure 38 Notes:
1. A one-clock-cycle wide pulse of nDATA_STRB (low) when nSELECT is
asserted (low) and valid address presented initiates the sequential burst
transfer. nSELECT must be asserted low through the full burst cycle. The
nDATA_RDY output is initially asserted low on the clock cycle prior to the
cycle in which the Total-AceXtreme® reads the first data word from the data
bus. CPU_nLAST must be asserted high until the last word is to be written. On
the rising clock edge following CPU_nLAST asserting low, the Total-
AceXtreme reads the last word from the data bus, and nDATA_RDY is de-
asserted (high). At this time (or later) nSELECT must be de-asserted high,
completing the burst write transfer.
2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data
memory word(s) are to be written. If either or both of these bits is ‘0’, then the
corresponding 16-bit word(s) will not be written. These inputs should be tied
high if unused. For register transfers, the value of CPR_WORD_EN[1:0] must
be ‘11’.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.
CPU_
DATA
HOST_
CLK
nDATA_RDY
CPU_WORD
_
EN[
1:
0
]
RD_nWR
MEM_nREG
CPU_
ADDR
nDATA_
STRB
nSELECT
CPU_nLAST
CPU_nSTOP
tRDD
tCLK
tDH
tRDD
tAS
tCS
tSH
tCH
Data
Data
Data
Data
Data
Data
Data
Data
tLS
tLH
tDS
Address
tWait
Data
tDH
tAS
tAS
tAS
tAH
tAH
tAH
tAH
tLS
tLH
tSS
tSHC