DDC Total-AceXtreme MIL-STD-1553 - Figure 16. Asynchronous Multiplexed Address 32-Bit Write Timing

HOST INTERFACE
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Figure 16. Asynchronous Multiplexed Address 32-bit Write Timing
Figure 16 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle. In
Asynchronous mode, nSELECT may be kept low for consecutive transactions
by the Total-AceXtreme.
2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data
memory words are to be written. If either or both these bits is ‘0’, then the
corresponding 16-bit word(s) will not be written. These inputs should be tied
high if unused.
3. For register accesses, the value of CPU_WORD_EN[1:0] must be ‘11’.
tDH
tDS
tALP
tSS
tAH
CPU
_
DATA
ADDR_LAT
nSELECT
nDATA_STRB
tSH
nDATA_
RDY
RD
_
nWR
MEM
_nREG
tRDDtWait
Data
tAH
CPU
_WORD
_EN
[
1:
0
]
tAH
tAH
tAS
tAS
Address
tAS
tAS