DDC Total-AceXtreme MIL-STD-1553 - External Fiber Optic Transceiver Interface

HOST INTERFACE
Data Device Corporation DS-BU-67301B-G
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Table 14. PCI Timing Information
REF DESCRIPTION NOTES
Timing Characteristics
UNITS
MIN TYP MAX
t
WRITE
FRAME# to TRDY# delay for a slave write cycle 4•t
CLK
ns
t
READ
FRAME# to TRDY# delay for a slave write cycle 66MHz
or
33MHz
5 t
CLK
+
50
6•t
CLK
+
75
ns
t
DMA_START
Falling edge of TRDY# for the write to start the
DMA to the falling edge of REQ# for the first
DMA transfer
66MHz
33MHz
330
540
390
660
ns
ns
Figure 49. PCI Parametric Timing
Figure 50. PCI Slave Burst Write
t
D
t
CLK
t
H
t
S
INPUT
OUTPUT
HOST_CLK
Input Valid
Output Valid
t
D
t
HZ
TRDY#
DEVSEL#
IRDY#
C/BE[3:0]#
FRAME#
tCLK
AD[31:0]
HOST_CLK
Data
Data
Data
Address
0x7
0x0
Data
tWrite