DDC Total-AceXtreme MIL-STD-1553 - Figure 17. Asynchronous Multiplexed Address 16-Bit Read Timing

HOST INTERFACE
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Figure 17. Asynchronous Multiplexed Address 16-bit Read Timing
Figure 17 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle. In
Asynchronous mode, nSELECT may be kept low for consecutive transactions
by the Total-AceXtreme.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full
transfer cycle.
tAH
MEM_nREG
tAH
nDATA_
RDY
CPU_
DATA
ADDR_LAT
nDATA_STRB
nSELECT
MSW_nLSW
RD_nWR
tRDD
tSS tSH
tWait tRDDtWait
Data A
tOHZ
tOH
tOHZ
tOH
tAS
tAS
Data B
tAS
Address
tAH
tALP
tAS
tDD tDD
tAS
tAS
Address
tALP
tAH
CPU_WORD_EN[1:0]
tAS tAH
tAH