DDC Total-AceXtreme MIL-STD-1553 - Figure 13. Asynchronous Non-Multiplexed Address 16-Bit Read Timing

HOST INTERFACE
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Figure 13. Asynchronous Non-Multiplexed Address 16-bit Read Timing
Figure 13 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle. In
Asynchronous mode, nSELECT may be kept low for consecutive transactions
by the Total-AceXtreme.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full
transfer cycle.
3. For register accesses, the value of CPU_WORD_EN[1:0] must be ‘11’.
CPU_WORD_EN[1:0]
MEM_nREG
MSW_nLSW
nDATA_RDY
CPU_DATA
CPU_ADDR
nDATA_STRB
nSELECT
RD_nWR
tRDD
tSS
tSH
tWait
tRDD
tWait
Data A
tOHZ
tOH
tOHZ
tOH
tAS
tAS
tAS
tAS
Data B
tDD
tAH
tAH
tAH
Address
tAS
tAH
tAS
tAH
tDD