HOST INTERFACE
Data Device Corporation DS-BU-67301B-G
www.ddc-web.com
1/14
Figure 34. Synchronous, Multiplexed Address 16-bit Single-Word Register Read Timing
Figure 34 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle, and
de-asserted high at the end of the transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full
transfer cycle.
3. For a register read access, CPU_nSTOP asserts (low) simultaneous with
nDATA_RDY, and de-asserts (high) on the host clock cycle following
nSELECT returning high.
CPU_WORD_EN[1:0]
CPU_DATA
nDATA_RDY
RD_nWR
MSW_nLSW
ADDR_LAT
nDATA_STRB
nSELECT
HOST_CLK
CPU_nSTOP
MEM_nREG
tAH
tDD
Data A
tWait tWait
Data B
tRDD tRDD tRDD
tOHZ
tOH
tOHZ
tOH
tAH
tDD
tCLK
tAS
tAS
tAS tAH
tAS
tAS tAH
tRDD
tALH
tALS
tCS
tSH
tSS
tALH
tALS
tCS
tSH
tSS
tCH tCH
tSTPD tSTPD tRDD tRDD
tAS tAH tAS tAH
Address
tAH
tAS
Address
tSHC
CPU_nLAST
To Next Page
Loading...
Need help?
General