DDC Total-AceXtreme MIL-STD-1553 - Figure 18. Asynchronous Multiplexed Address 16-Bit Write Timing

HOST INTERFACE
Data Device Corporation DS-BU-67301B-G
www.ddc-web.com
1/14
50
Figure 18. Asynchronous Multiplexed Address 16-bit Write Timing
Figure 18 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle. In
Asynchronous mode, nSELECT may be kept low for consecutive transactions
by the Total-AceXtreme.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full
transfer cycle.
RD_nWR
MSW_nLSW
nSELECT
tAH
tRDD
tSS
tSH
tWait
tRDD
nDATA_RDY
CPU_DATA
ADDR_LAT
nDATA_STRB
tAS
tAS
tAS
Address
tALP
Data A
Data B
tDS
tDH
tDS
tDH
tWait
tAH
tAS
tAS
Address
tALP
tAH
tAH
CPU_WORD_EN[1:0]
MEM_nREG
tAS
tAS
tAH
tAH