DDC Total-AceXtreme MIL-STD-1553 - MIL-STD-1553 Transceiver Options; Using Internal Transceivers and Transformers

HOST INTERFACE
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Table 13. PCI Bus Interface Signals
Signal Name DIR Description
HOST_CLK I
PCI Clock
Input clock from the host. Can be up to 66MHz
PCI_AD[31:0] I/O
PCI Address / Data
GNT# I
Bus Master Grant
Indicates to the Total-AceXtreme that access to the bus has been
granted by the PCI Arbiter. This is only required for DMA/PCI Initiator
transactions.
REQ# O
Bus Master Request
Request to the bus Arbiter for control of the PCI bus. This is only
required for DMA/PCI Initiator transactions.
PERR# I/O
Parity Error
This pin is used for reporting parity errors. It does not indicate Parity
errors during the Address phase.
IDSEL I
Initialization Device Select
This signal is used as a chip select during configuration read or write
operations. It should be connected to an upper PCI A/D line or an
individual control signal from the PCI Bus Controller. The connection is
system specific.
DEVSEL# I/O
Device Select
This signal is sourced by the active target upon decoding that its address
and bus commands are valid.
STOP# I/O
PCI Stop.
This signal indicates the current target is requesting the master to
stop the current transaction.
IRDY# I/O
Initiator Ready
This signal indicates that the initiating agent is able to complete the
current data phase of the transaction.
TRDY# I/O
PCI Target Ready
This signal indicates the ability of the target agent’s (selected device)
ability to complete the current data phase of the transaction.
FRAME# I/O
PCI Frame
This signal is driven by the current master to indicate the
beginning and duration of an access.
PAR I/O
PCI Parity
This signal represents even3 parity across AD[31::00] and C/BE[3::0]#.
C/BE[3:0]# I/O
PCI Command and Byte Enables
These signals are multiplexed on the same PCI pins. During the address
phase of a transaction, C/BE[3::0]# define the bus command.
During the data phase, C/BE[3::0]# are used as Byte Enables.
SERR# I/O
PCI System Error
This signal is used for reporting address parity errors, data parity
errors on the Special Cycle command, or any other system
error where the result will be catastrophic.
INTA# O
Interrupt
This pin is a level sensitive, active low interrupt to the host.