DDC Total-AceXtreme MIL-STD-1553 - Figure 31. Synchronous, Multiplexed Address 32-Bit - Single-Word Register Read Timing

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HOST INTERFACE

Data Device Corporation DS-BU-67301B-G

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Figure 31. Synchronous, Multiplexed Address 32-bit - Single-Word Register Read

Timing

Figure 31 Notes:

1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this

data transfer. nSELECT must be asserted through the full transfer cycle, and

de-asserted high at the end of the transfer.

2. For register accesses, the value of the CPU_WORD_EN[1:0] inputs must be

‘11’.

3. For a register read access, CPU_nSTOP asserts (low) simultaneous with

nDATA_RDY, and de-asserts (high) on the host clock cycle following

nSELECT returning high.

CPU_nLAST

nDATA

_RDY

CPU

_DATA

CPU

_WORD

_EN[1:0]

_nWR

MEM

_nREG

ADDR_

LAT

nDATA

_STRB

nSELECT

CPU_

nSTOP

HOST

_CLK

tOHZ

tOH

tSTPD

tDD

tCLK

tRDD

tSTPD

Address

Data

tAH

tALS

tAH

tSH

tSS

tCS

tCH

tALH

tAS

tAH

tSHC

tWait

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DDC Total-AceXtreme MIL-STD-1553 - Figure 31. Synchronous, Multiplexed Address 32-Bit - Single-Word Register Read Timing

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