DDC Total-AceXtreme MIL-STD-1553 - Figure 36. Synchronous, Multiplexed Address 16-Bit Single-Word Register Write Timing

HOST INTERFACE
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Figure 36. Synchronous, Multiplexed Address 16-bit Single-Word Register Write Timing
Figure 36 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle, and
de-asserted high at the end of the transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full
transfer cycle.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted for write accesses, and will remain high.
CPU_WORD_EN[1:0]
CPU_DATA
nDATA_RDY
RD_nWR
ADDR_LAT
nDATA_STRB
nSELECT
HOST_CLK
MSW_nLSW
MEM_nREG
CPU_nSTOP
tDS tDH
tWait
tWait
tRDD
tRDD
tRDD
tRDD
tCLK
tAS
Address
tAH
tALH
tALS
tALH
tALS
tCS
tSH
tSS
tCS
tSH
tSS
tCH
tAS
tAH
tAS
tAS
tAS
tAS
tAH
tAH
tAH
tSHC
tCH
tAS
Address
tAH
Data A
Data B
tDS
tDH
tAS
tAH