DDC Total-AceXtreme MIL-STD-1553 - Figure 25. Synchronous, Non-Multiplexed Address - 32-Bit Single-Word Write Timing

HOST INTERFACE
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Figure 25. Synchronous, Non-Multiplexed Address - 32-bit Single-Word Write Timing
Figure 25 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle, and
de-asserted high at the end of the transfer.
2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data
memory words are to be written. If either or both these bits is ‘0’, then the
corresponding 16-bit word(s) will not be written to Total-AceXtreme memory.
These inputs should be tied high if unused. For register transfers, the value of
CPU_WORD_EN[1:0] must be ‘11’.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted for memory accesses, and will remain high.
nDATA_RDY
CPU_DATA
CPU_WORD_EN[1:0]
RD_nWR
MEM_nREG
CPU_ADDR
nDATA_STRB
nSELECT
HOST_CLK
CPU_nSTOP
tDHtDS
tAS
tCLK
Address
tRDD tRDD
tSH
tSS
tCS tCH
Data
tWait
tAS
tAS
tAS
tAH
tAH
tAH
tAH
tSHC
CPU_nLAST