DDC Total-AceXtreme MIL-STD-1553 - Figure 46. Synchronous, Multiplexed Address - 16-Bit Sequential Burst Write Transfer Timing

HOST INTERFACE
Data Device Corporation DS-BU-67301B-G
www.ddc-web.com
1/14
86
Figure 46. Synchronous, Multiplexed Address - 16-bit Sequential Burst Write Transfer
Timing
Figure 46 Notes:
1. With nSELECT asserted low and valid address presented on CPU_DATA, a
positive pulse on the ADDR_LAT input satisfying t
ALS
and T
AHL
will result in the
Total-AceXtreme® latching the starting address for the sequential burst. One
clock cycle later, a one-clock-cycle wide pulse of nDATA_STRB (low) while
nSELECT remains asserted (low) initiates the sequential burst transfer.
nSELECT must be asserted low through the remainder of the burst cycle. The
nDATA_RDY output is initially asserted low on the clock cycle prior to the
cycle in which the Total-AceXtreme reads the first 16-bit data word from the
data bus. CPU_nLAST must be asserted high until the last 16-bit word is to be
written. On the rising clock edge following CPU_nLAST asserting low, the
Total-AceXtreme reads the last 16-bit word from the data bus, and
nDATA_RDY is de-asserted (high). At this time (or later) nSELECT must be
de-asserted high, completing the burst write transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full
transfer cycle.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.
MSW_nLSW
nDATA
_RDY
CPU_DAT
A
HOST_
CLK
CPU_WORD_EN[1:0
]
RD_nWR
MEM_nREG
ADDR
_
LAT
nDATA_
STRB
nSELECT
CPU
_nLAST
CPU_nSTOP
tCLK
tDH
tDS
tRDD
tCS
tALS
tALH
tRDD
tDH
tCH
tAH
Data Data Data Data Data
Data Data Data
tAH
Data
tAH
tAH
Data
Address
tAS
tAH
tAS
tAH
tLS
tSS
tSH
tAS
tAS
tAS
tLH
tLS
tWait
tSHC