DDC Total-AceXtreme MIL-STD-1553 - Figure 33. Synchronous, Multiplexed Address 16-Bit - Single-Word Memory Read Timing

HOST INTERFACE
Data Device Corporation DS-BU-67301B-G
www.ddc-web.com
1/14
73
Figure 33. Synchronous, Multiplexed Address 16-bit - Single-Word Memory Read
Timing
Figure 33 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle, and
de-asserted high at the end of the transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full
transfer cycle.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted for memory accesses, and will remain high.
CPU_DATA
nDATA_RDY
RD_nWR
MSB_nLSW
ADDR_LAT
nDATA_STRB
nSELECT
HOST_CLK
MEM_nREG
CPU_WORD_EN[1:0]
CPU_nSTOP
tAH
tDD
Data A
tWait tWait
Data B
tOHZ
tOH
tOHZ
tOH
tAH
tDD
tCLK
tAS
tAS
tAS tAH
tAS
tAS tAH
tALH
tALS
tCS
tSH
tSS
tALH
tALS
tCS
tSH
tSS
tCH tCH
tSTPD tSTPD tRDD tRDD
tAS tAH tAS tAH
Address Address
tAH
tSHC
tAS
CPU_nLAST