DDC Total-AceXtreme MIL-STD-1553 - Figure 39. Synchronous, Non-Multiplexed Address 32-Bit - Random Burst Write Transfer Timing

HOST INTERFACE
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Figure 39. Synchronous, Non-Multiplexed Address 32-bit - Random Burst Write
Transfer Timing
Figure 39 Notes:
1. For a random burst write transfer, both nDATA_STRB and nSELECT must be
asserted low through the entire time of the transfer. The nDATA_RDY output
is initially asserted low on the clock cycle prior to the cycle in which the Total-
AceXtreme® reads the first data word from the data bus. CPU_nLAST must
be asserted high until the last word is to be written. On the rising clock edge
following CPU_nLAST asserting low, the Total-AceXtreme reads the last
word from the data bus, and nDATA_RDY is de-asserted (high). At this time
(or later) nDATA_STRB and nSELECT must be de-asserted high, completing
the burst write transfer.
2. The CPU_WORD_EN[1:0] inputs are used to specify which bit data memory
word(s) are to be written. If either or both of these bits is ‘0’, then the
corresponding 16-bit word(s) will not be written. These inputs should be tied
high if unused.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.
CPU_DATA
HOST_
CLK
nDATA_RDY
CPU_WORD_EN[1:0]
RD_nWR
MEM_nREG
CPU_ADDR
nDATA_STRB
nSELECT
CPU_nLAST
CPU_nSTOP
tAS
Address
Address
tAH
tRDD
tLS
tCLK
tAS
tAS
tDH
tSH
Address
Address
Address Address
Address Address Address
tCS
tSS
tRDD
tAH
tAH
tCH
Data Data
Data Data
Data Data Data DataData
tDS
tAH
tAH
tLH
tLS
tLH
tWait
tDH
tSHC