DDC Total-AceXtreme MIL-STD-1553 - Figure 29. Synchronous, Non-Multiplexed Address - 16-Bit Single-Word Register Write Timing

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HOST INTERFACE

Data Device Corporation DS-BU-67301B-G

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Figure 29. Synchronous, Non-Multiplexed Address - 16-bit Single-Word Register Write

Timing

Figure 29 Notes:

1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this

data transfer. nSELECT must be asserted through the full transfer cycle, and

de-asserted high at the end of the transfer.

2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full

transfer cycle.

3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not

asserted for write accesses, and will remain high.

nDATA_RDY

nSELECT

CPU_ADDR

nDATA_STRB

CPU_DATA

HOST_CLK

MSW_nLSW

RD_nWR

CPU_WORD_EN[1:0]

MEM_nREG

CPU_nSTOP

tDS

tAS tAH

tDH

tCLK tWait tWait

tRDD tRDD tRDD

tAS

tSS

tCS

tSS

tCStCH tCH

tSH tSH

Data A Data B

tAS

tDS tDH

tAH

tSHC

tRDD

Address

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DDC Total-AceXtreme MIL-STD-1553 - Figure 29. Synchronous, Non-Multiplexed Address - 16-Bit Single-Word Register Write Timing

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