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DDC Total-AceXtreme MIL-STD-1553 - Figure 27. Synchronous, Non-Multiplexed Address 16-Bit - Single-Word Register Read Timing

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Data Device Corporation DS-BU-67301B-G
www.ddc-web.com
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Figure 27. Synchronous, Non-Multiplexed Address 16-bit - Single-Word Register Read
Timing
Figure 27 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle , and
de-asserted high at the end of the transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full
transfer cycle.
3. For a register read access, CPU_nSTOP asserts (low) simultaneous with
nDATA_RDY, and de-asserts (high) on the host clock cycle following
nSELECT returning high.

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