DDC Total-AceXtreme MIL-STD-1553 - Figure 15. Asynchronous Multiplexed Address 32-Bit Read Timing

HOST INTERFACE
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Figure 15. Asynchronous Multiplexed Address 32-bit Read Timing
Figure 15 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle. In
Asynchronous mode, nSELECT may be kept low for consecutive transactions
by the Total-AceXtreme.
2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data
memory words are valid for this transfer. If either or both these bits is ‘0’, then
the corresponding 16-bit word(s) will return a value of ‘0000’. These inputs
should be tied high if unused.
3. For register accesses, the value of CPU_WORD_EN[1:0] must be ‘11’.
tALP
tSS
tAH
CPU_DATA
ADDR_LAT
nSELECT
nDATA_STRB
nDATA_RDY
RD_nWR
MEM_nREG
tRDDtWait
tAH
Data
tOH
tSH
tOHZtDD
CPU_WORD_EN[1:0]
tAH
tAH
Address
tAS
tAS
tAS
tAS