HOST INTERFACE
Data Device Corporation DS-BU-67301B-G
www.ddc-web.com
1/14
6.5 PCI Interface
In addition to the flexible parallel CPU interface, the Total-AceXtreme® also includes
a PCI 2.3 compliant Target/Initiator interface. Table 12 lists the features and
characteristics of the Total-AceXtreme’s PCI interface.
Table 12. Total-AceXtreme® PCI Interface Characteristics
PCI Characteristic/Feature Total-AceXtreme®
PCI Specification Compliance Revision 2.3
Maximum PCI clock frequency 66 MHz
Support 32-bit PCI Bus YES
Support 64-bit PCI Bus (AD[63::32]) NO
3.3V Signaling YES
5V Tolerant NO
PCI Target Interface YES
PCI Initiator Interface YES
Single-Channel PCI Initiator/DMA Engine Memory only, not registers
PCI Initiator/DMA Engine: Transfer Directions Supports transfers in both directions: host-to-Total-
AceXtreme and Total-AceXtreme -to-host.
PCI Initiator/DMA Engine: Data Transfer Modes
• Block transfer mode (single descriptor execution
via registers).
• Scatter/gather mode (descriptors stored in host
memory)
PCI Initiator/DMA Engine: PCI burst lengths Programmable (including infinite)
PCI Initiator/DMA Engine: PCI Retry timeout Programmable (including infinite)
PCI Initiator/DMA Engine: Programmable Interrupts
• DMA Complete
• DMA Descriptor Done
• DMA Abort Function via register control
Memory and Register Addressability
• DWord or Word write accesses to memory
• DWord write accesses to registers
• DWord or Word read accesses from registers
• No 8-bit accesses
Interrupts supported INTA#
PCI Retries Supported
Disconnect with Data Supported
Target Abort Total-AceXtreme will never generate a target abort
Delayed Transactions Supports up to two simultaneous
BAR0/BAR1 Support BAR0 = Total-AceXtreme Memory
BAR1 = Total-AceXtreme Registers
Zero wait state bursts Supported, for both reads and writes as both Target
and Initiator
To Next Page
Loading...
Need help?
General