HOST INTERFACE
Data Device Corporation DS-BU-67301B-G
www.ddc-web.com
1/14
Table 13. PCI Bus Interface Signals
Signal Name DIR Description
RST# I
PCI Reset
Negative true Reset input, normally asserted low following power turn-on.
This input conforms to PCI RST# convention.
6.5.4 PCI Target Interface
The Total-AceXtreme’s PCI Target interface supports a similar set of data transfer
capabilities as the Synchronous parallel CPU interface. These include:
• 32-bit read and write operations to registers and memory.
• 16-bit memory write operations.
• Sequential reads from registers are not supported.
Table 14 lists the timing parameters for the Total-AceXtreme’s PCI interface. Figure
49 through Figure 51 illustrate the timing for the Total-AceXtreme’s PCI Target
interface.
6.5.4.1 PCI Target STOP# Assertion
Similar to the Synchronous parallel CPU interface, the Total-AceXtreme® posts all
requests to read or write individual words on to a command FIFO. As described in
paragraph 6.4.2, it is possible to fill the FIFO by means of a burst write transfer to
Total-AceXtreme registers. Since burst transfers can write to the command FIFO at
up to 66 MHz and register writes are drained at only a 40 MHz rate, it is possible to
incur a FIFO overflow condition. When this occurs, the Total-AceXtreme’s PCI
Target interface will terminate the current transaction by asserting its STOP# output
low.
Table 14. PCI Timing Information
REF DESCRIPTION NOTES
Timing Characteristics
UNITS
MIN TYP MAX
f
CLK
HOST_CLK frequency 66 MHz
t
CLK
HOST_CLK cycle time 15 ns
t
S
Input setup time 3 ns
t
H
input hold time 0 ns
t
D
output valid delay 10pF
load
2 6 ns
t
HZ
output high-z delay 10pF
load
14 ns
To Next Page