DDC Total-AceXtreme MIL-STD-1553 - 11.4 Total-Acextreme Pin Diagram; Figure 61. Total-Acextreme Pin Diagram

TOTAL- ACEXTREME® SIGNALS
Data Device Corporation DS-BU-67301B-G
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11.4 Total-AceXtreme® Pin Diagram
A B
C
D E
F G
H
J
K L
M
N
P R T
U V
18
NC NC
NC
CHA_15
53_L
CHA_15
53_L
CHA_15
53
CHA_15
53
NC
NC NC
NC
NC
CHB_15
53
CHB_15
53
CHB_15
53_L
CHB_15
53_L
NC NC
18
17
NC NC NC
CHA_15
53_L
CHA_15
53_L
CHA_15
53
CHA_15
53
NC NC NC NC NC
CHB_15
53
CHB_15
53
CHB_15
53_L
CHB_15
53_L
NC NC
17
16
NC
NC NC
NC NC NC NC NC
NC
NC NC
NC NC NC NC NC
NC
NC
16
15
GND_
LOGIC
NC
NC NC
NC NC NC NC
NC NC
NC NC
NC NC NC NC
NC
GND_
LOGIC
15
14
GND_
LOGIC
GND_
LOGIC
DISAB
_BC
DISAB
_MULT
_RT
GND_
LOGIC
GND_
LOGIC
RTAD
0
RTAD
4
GND_
LOGIC
GND_
LOGIC
DISC
IO (6)
DISC
IO (0)
IRIG_
DIG_IN
TX_INH
_B
nSSFLA
G
NC
GND_
LOGIC
GND_
LOGIC
14
13
PLL_LOC
KED
GND_
LOGIC
DISAB_B
IST
nRT
BOOT
TEMP_
DIODE
GND_
LOGIC
RTAD
1
RTAD
P
DISC
IO (4)
DISC
IO (1)
DISC
IO (3)
TAG_
CLK
TAG_
ENABLE
TX_INH
_A
nSNGE
ND
USER_
OUT_1
USER_
OUT_2
NC
13
12
GND_
LOGIC
GND_
LOGIC
+3.3V
LOGIC
NC
GND_
XCVR
GND_
XCVR
RTAD
3
DISC
IO (7)
DISC
IO (5)
DISC
IO (2)
nMCRST/
nINCMD
TAG_LO
AD
NC
GND_
XCVR
GND_
XCVR
NC NC
NC
12
11
GND_
LOGIC
GND_
LOGIC
PCI_nC
PU
GND_
LOGIC
GND_
XCVR
GND_
XCVR
RT_AD
_LAT
TXINH_
IN_A
TXDATA
_OUT_A_
L
TXDATA
_IN_A_L
TXINH_
OUT_B
TXINH
_IN_B
NC
GND_
XCVR
GND_
XCVR
EXT_
TRIG
NC NC
11
10
JTAG
TMS
JTAG
TDI
nPOR
+3.3V
LOGIC
GND_
LOGIC
GND_
LOGIC
RTAD
2
TXINH_
OUT_A
TXDATA
_OUT_A
TXDATA
_IN_A
TXDATA
_OUT_B
TXDATA
_IN_B
NC NC
NC NC
+3.3V
XCVR
GND_
XCVR
10
9
PCI_INT
A#
JTAG
nTRST
+3.3V
LOGIC
GND_LO
GIC
GND_
LOGIC
GND_
LOGIC
GND_
LOGIC
+3.3V
LOGIC
RXDATA
_IN_A_L
RXDATA_
OUT_A_L
TXDATA
_OUT_B_
L
TXDATA
_IN_B_L
+3.3V
XCVR
GND_
XCVR
GND_
XCVR
+3.3V
XCVR
NC NC
9
8
CLOCK_I
N
JTAG
TDO
+3.3V
LOGIC
GND_
LOGIC
1.8V
PLL
1.8V
CORE
GND_
LOGIC
+3.3V
LOGIC
RXDATA
_IN_A
RXDATA
_OUT_A
TRIG_
SEL
NC
+3.3V
XCVR
GND_
XCVR
GND_
XCVR
+3.3V
XCVR
NC NC
8
7
JTAG
TCK
PCIREQ#/
CPU_ADD
R(12)
+3.3V
LOGIC
GND_
LOGIC
1.8V
CORE
1.8V
CORE
GND_
LOGIC
+3.3V
LOGIC
CPU_AS
YNC_nS
YNC
POL_
SEL
CPU_
AD_
MULTI
+3.3V
LOGIC
+3.3V
XCVR
GND_
XCVR
GND_
XCVR
+3.3V
XCVR
RXDATA
_IN_B_L
RXDATA_
OUT_B_L
7
6
PCI_GNT#
/CPU_AD
DR (13)
RST#/
nMSTCLR
+3.3V
LOGIC
GND_
LOGIC
1.8V
CORE
1.8V
CORE
GND_
LOGIC
+3.3V
LOGIC
RD_
nWR
DATA32
_n16
MSW_
nLSW
nDATA_
STRB
+3.3V
XCVR
GND_
XCVR
GND_
XCVR
+3.3V
XCVR
RXDATA
_IN_B
RXDATA
_OUT_B
6
5
PCI_AD31/
DATA31
PCI_AD29/
DATA29
+3.3V
LOGIC
GND_
LOGIC
1.8V
CORE
1.8V
CORE
GND_
LOGIC
+3.3V
LOGIC
PCI_AD17/
DATA17
C/BE1#/C
PU_ADDR
(1)
PCI_AD0/
DATA0
PCI_AD3/
DATA3
+3.3V
XCVR
GND_
XCVR
GND_
XCVR
+3.3V
XCVR
NC NC
5
4
PCI_AD30/
DATA30
PCI_AD28/
DATA28
+3.3V
LOGIC
GND_
LOGIC
GND_
LOGIC
GND_
LOGIC
GND_
LOGIC
+3.3V
LOGIC
C/BE2#/C
PU_ADDR
(2)
PCI_AD1/
DATA1
PCI_AD2/
DATA2
PCI_AD5/
DATA5
PCI_AD6/
DATA6
CPU_W
DEN1
CPU_
nBLAST
CPU_A
DDR15
NC NC
4
3
NC
PCI_AD27/
DATA27
PCI_IRDY
#/CPU_AD
DR(7)
PCI_AD24/
DATA24
PCI_AD21/
DATA21
PCI_AD20/
DATA20
PCI_AD18/
DATA18
PCI_FRA
ME#/CPU_
ADDR(5)
PCI_TRDY
#/CPU_AD
DR(6)
PCI_AD4/
DATA4
PCI_AD11/
DATA11
C/BE0#/
CPU_A
DDR(0)
PCI_AD7/
DATA7
CPU_W
DEN0
ADDR_L
AT
CPU_A
DDR14
NC NC
3
2
NC NC
PCI_AD25/
DATA25
PCI_IDSE
L/CPU_AD
DR(10)
PCI_AD22/
DATA22
HOST_
CLK
PCI_PERR
#/CPU_AD
DR(11)
PCI_STOP
#/CPU_AD
DR(8)
PCI_SE
RR#
PCI_AD10/
DATA10
PCI_PAR/
CPU_ADD
R(4)
PCI_AD14/
DATA14
PCI_AD8/
DATA8
nINT
MEM_
nREG
nSELEC
T
NC NC
2
1
NC NC NC
PCI_AD26/
DATA26
C/BE3#/C
PU_ADDR
(3)
PCI_AD23/
DATA23
PCI_AD19/
DATA19
PCI_AD16/
DATA16
DEVSEL#/
CPU_ADD
R(9)
PCI_AD15/
DATA15
PCI_AD13/
DATA13
PCI_AD9/
DATA9
PCI_AD12/
DATA12
CPU_
nSTOP
nDATA_
RDY
NC NC NC
1
A B C D
E
F G H
J
K L
M
N
P
R
T U V
CPU BUS
MISC
CONFIG PAD (STATIC)
MCM BALL LAYOUT LOOKING TOP DOWN THRU MCM
PCI BUS
1553 MISC
TEST / PROGRAM PAD
XCVR MISC
Figure 61. Total-AceXtreme® Pin Diagram