DDC Total-AceXtreme MIL-STD-1553 - Table 8. Synchronous 16-Bit Mode Configuration Options

HOST INTERFACE
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Table 8. Synchronous 16-bit Mode Configuration Options
POL_SEL RD_nWR FIRST WORD TRANSFER
SECOND WORD
TRANSFER
1 1
MSW_nLSW = 1
CPU  RAM 15:0
MSW_nLSW = 0
CPU  RAM 31:16
1 0
MSW_nLSW = 1
CPU  RAM 15:0
MSW_nLSW = 0
CPU  RAM 31:16
0 1
MSW_nLSW = 0
CPU  RAM 15:0
MSW_nLSW = 1
CPU  RAM 31:16
0 0
MSW_nLSW = 0
CPU  RAM 15:0
MSW_nLSW = 1
CPU  RAM 31:16
6.4.4.1 Synchronous Mode Connection Diagrams
Figure 19 through Figure 22 show the four possible Synchronous mode interface
configurations, including the four combinations of 32-bit, 16-bit, non-multiplexed, and
multiplexed.