DDC Total-AceXtreme MIL-STD-1553 - Figure 24. Synchronous, Non-Multiplexed Address - 32-Bit Single-Word Register Read Timing

HOST INTERFACE
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Figure 24. Synchronous, Non-Multiplexed Address - 32-bit Single-Word Register Read
Timing
Figure 24 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT should be asserted throughout the entire transfer
cycle, and de-asserted high at the end of the transfer.
2. For register transfers, the value of the CPU_WORD_EN[1:0] inputs must be
‘11’.
3. For a single-word register read access, CPU_nSTOP asserts (low)
simultaneous with nDATA_RDY, and de-asserts (high) on the host clock cycle
following nSELECT returning high.
nDATA
_RDY
CPU_
DATA
CPU
_
WORD
_EN
[
1
:
0
]
RD
_nWR
MEM
_
nREG
CPU
_
ADDR
nDATA
_
STRB
nSELECT
CPU_
nSTOP
HOST_
CLK
tOHZ
tOH
tSTPD
tDD
tSH
Address
tCLK
Data
tRDD
tRDD
tSTPD
tSS
tCS
tCH
tAS
tAS
tAS
tAS
tAH
tAH
tAH
tAH
tSHC
tWait
CPU
_nLAST