DDC Total-AceXtreme MIL-STD-1553 - Table 19. CPU Data Bus

TOTAL- ACEXTREME® SIGNALS
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Table 18. PCI Signals
Signal Name BALL Pullup/
Pulldown
Description
C/BE[3]# (I/O) E1 None Bus Command and Byte Enables. These signals are multiplexed on the same
pins. During the address phase of a bus operation, these pins identify the bus
command, as shown in the table below. During the data phase of a bus
operation, these pins are used as Byte Enables, with C/BE[0]# enabling byte
0 (LSB) and C/BE[3]# enabling byte 3 (MSB). The Total-AceXtreme responds
to the following PCI commands
C/BE[3:0]# Description (during address phase)
0 1 1 0 - Memory Read
0 1 1 1 - Memory Write
1 0 1 0 - Configuration Read
1 0 1 1 - Configuration Write
1 1 0 0 - Memory Read Multiple
1 1 1 0 - Memory Read Line
1 1 1 1 - Memory Write and Invalidate
Note that the last three memory commands are aliased to the basic memory
commands: Memory Read and Memory Write.
C/BE[2]# (I/O) J4 None
C/BE[1]# (I/O) K5 None
C/BE[0]# (I/O) M3 None
SERR# (I/O) J2 None System Error. This pin is used for reporting address parity errors, data parity
errors on Special Cycle commands, or any other condition having a
catastrophic system impact.
INTA# (O) A9 None Interrupt A. This pin is a level sensitive, active low interrupt to the host
RST# (I) B6 None PCI Reset. Negative true Reset input, normally asserted low following power
turn-on. This input conforms to PCI RST# convention. Asserting RST# low
resets all internal logic, including the PCI interface. However, this signal does
not reset the PLL that generates the internal 160 MHz clock.
11.2.2 FGPI Signals
Table 19. CPU Data Bus
Signal Name BAL
L
Pullup/
Pulldown
Description
CPU_DATA(31) (I/O) MSB A5 None
32-Bit bi-directional CPU Data Bus. This bus interfaces the host processor to
the Total-AceXtreme internal registers and internal RAM. Most of the time, the
outputs for DATA31 through DATA00 are in the high impedance state. They
drive outward when the host CPU reads the internal RAM or registers.
CPU_DATA[31:16] are only used when the 32-bit mode is enabled.
For the multiplexed address/data mode, CPU_DATA(15:0) operate as the
address bus inputs during the first (address) portion of a transfer cycle.
CPU_DATA(30) (I/O) A4 None
CPU_DATA(29) (I/O) B5 None
CPU_DATA(28) (I/O) B4 None
CPU_DATA(27) (I/O) B3 None
CPU_DATA(26) (I/O) D1 None
CPU_DATA(25) (I/O) C2 None