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HOST INTERFACE

Data Device Corporation DS-BU-67301B-G

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Figure 30. Synchronous, Multiplexed Address 32-bit - Single-Word Memory Read

Timing

Figure 30 Notes:

1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this

data transfer. nSELECT must be asserted through the full transfer cycle, and

de-asserted high at the end of the transfer.

2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data

memory words are to be read for this transfer. If either or both these bits is ‘0’,

then the corresponding 16-bit word(s) will return a value of ‘0000’. These

inputs should be tied high if unused.

3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not

asserted for memory accesses, and will remain high.

nDATA_RDY

CPU_DATA

CPU_WORD_EN[1:0]

RD_nWR

MEM_nREG

ADDR_LAT

nDATA_STRB

nSELECT

HOST_CLK

CPU_nSTOP

tOHZ

tCLK

tRDD

Data

tALS

tSH

tSS

tCS tCH

tALH

Address

tAH

tAS

tAH

tWait

tAH

tOH

tDD

tSHC

CPU_nLAST

Brand

DDC

Model

Total-AceXtreme MIL-STD-1553

DDC Total-AceXtreme MIL-STD-1553 User Manual

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Questions and Answers:

DDC Total-AceXtreme MIL-STD-1553 Specifications