DDC Total-AceXtreme MIL-STD-1553 - Figure 3. Bus Controller Block Diagram - Remote Terminal Operation

MIL- STD- 1553 MODES AND ARCHITECTURE
Data Device Corporation DS-BU-67301B-G
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Figure 3. Bus Controller Block Diagram - Remote Terminal Operation
The Total-AceXtreme® RT architecture builds upon the single-RT architecture of
Enhanced Mini-ACE, Mini-ACE Mark 3, Micro-ACE(TE), and Total-ACE.
One of the major new features of Total-AceXtreme is its Multi-RT capability. That is,
the Total-AceXtreme provides the capability to implement up to 31 independent
Remote Terminals (up to 32 RTs if Broadcast is disabled).
The Total-AceXtreme -RT engine can also be configured to operate in a Single-RT
legacy mode of operation. Single-RT operation supports hardware control of the RT
address and automatic boot, allowing the Total-AceXtreme to respond to commands
with Status with its Busy bit set immediately following power turn-on without requiring
configuration by the host.
For RT (and/or Monitor) applications, where the possibility of BC operation must be
absolutely prohibited, the Total-AceXtreme includes a DISABLE_BC input signal. In
addition to single-RT and Multi-RT operation, the Total-AceXtreme® includes the
following capabilities:
BC Block
Shared RAM (Applicable Logical Areas Highlighted)
Command Interpreter
LP Queue
Controller
HP Queue
Controller
BC Registers
1553 BC
Protocol
Engine
Instruction
List
(ICL)
Message
Blocks
(MB)
Data
Blocks
(DB)
HP Queue
(HPQ)
LP Queue
(LPQ)
General
Purpose Flags
(GPF)
General
Purpose
Queue
(GPQ)
1553_IN_A
1553_IN_B
1553_OUT_A
1553_OUT_B
R
E
G
I
n
t
e
r
f
a
c
e
M e
m
o r y B u s ( 3
2
- B
i t )
ICL
GPQ
HPQ
LPQ
MB/DB
MEM Interface
EXT_TRIG
GPQ Controller
Message Timer (16 bits)
1us
Delay Timer (16 bits)
1us