TOTAL- ACEXTREME® SIGNALS
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Table 19. CPU Data Bus
Signal Name BAL
L
Pullup/
Pulldown
Description
ADDR_LAT (I)
R3 50k
Pulldown
Address Latch.
When CPU_ADDR_MULTI equals ‘1’, this indicates that the address is
presented on CPU_DATA(15:0). For the case of synchronous multiplexed
mode, ADDR_LAT should be asserted high for one clock cycle of the host
clock.
For non-multiplexed mode, ADDR_LAT should be hardwired high .
DATA32_n16 (I) K6 50k Pullup Data Bus Select.
Indicates 32-bit mode when ‘1’ and 16-bit mode when ‘0’.
MSW_nLSW (I) L6 50k Pullup Most Significant Byte/Least Significant Byte.
In 16-bit modes, indicates the high ‘1’ or low ‘0’ word that is being transferred
(See POL_SEL). This signal should be active high or low throughout address
phase of transfer. Not used in 32-bit mode.
POL_SEL (I) K7 50k Pullup CPU Polarity Select.
Input which determines which word is “high” or “low”.
In 32-Bit Mode:
If ‘1’, RD_nWR has normal polarity, i.e. read is ‘1’ and write is ‘0’. If POL_SEL
is ‘0’ then RD_nWR* has inverted polarity, i.e. read is ‘0’ and write is ‘1’.
In 16-Bit Mode:
POL_SEL indicates which word is the most significant word.
If POL_SEL is ‘0’ then the least significant word has an address LSB of ‘0’ and
the most significant word has an address LSB of ‘1’.
If POL_SEL is ‘1’ then the least significant word has an address LSB of ‘1’ and
the most significant word has an address LSB of ‘0’. Static signal.
TRIG_SEL (I) L8 50k Pullup CPU Trigger Select input.
In 16-bit modes, indicates which 16-bit transfer will trigger a read or write
operation. When ‘1’ then the “high” order word triggers the transfer and when
‘0’ the low word triggers the transfer. This is used in conjunction with
POL_SEL which determines which word is “high” or “low”.
TRIG_SEL is not used in 32-bit mode or in Synchronous Mode.
MEM_nREG (I) R2 50k Pullup CPU Memory/Register.
Indicates the selection of memory space if ‘1’, or register space if ‘0’. This
signal should be active high or low throughout the address phase of transfer.
Total-AceXtreme registers are accessed by asserting MEM_nREG = ‘0’. Any
attempt to access a register location beyond address x“3FF” will result in a
rollover back to the beginning of the 8K register space.
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