OVERVIEW
Data Device Corporation DS-BU-67301B-G
www.ddc-web.com
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- 32-bit PCI Target/Initiator Interface
Operates at up to 66 MHz
Target single-word reads as low as 125 ns for reads, and 60 ns for
writes
Target Word Bursts at PCI Clock Rate
PCI Initiator with built-in DMA Engine with 264MB/sec Burst Transfer
Rate for reduced host resources.
• 1 Dual Redundant MIL-STD-1553 Channel
- BC or Multi-RT with Concurrent Bus Monitor
- Support of MIL-STD-1553 A/B, STANAG-3838, and MIL-STD-1760
- 2 Mb (64K x 36) RAM
- Transmit Inhibit Ball for Monitor-only Applications
- BC Disable Ball for RT-only Applications
- 48-bit/100ns Time Stamp
- IRIG-106 Chapter 10 Monitor
• 1553 Bus Controller (BC)
- Highly Autonomous Controller, with 32-Instruction Set
- Streaming and Minor/Major Frame Scheduling of Messages
- High and Low Priority Asynchronous Message Insertion
- Modify Messages or Data while BC is running
• 1553 Remote Terminal (RT)
- Emulate up to 31 RT Addresses Simultaneously
- Multiple Buffering Techniques
- Programmable Command Illegalization
- Programmable Busy by Sub-address
- RT Auto-Boot Option for MIL-STD-1760
• 1553 Bus Monitor (MT)
- IRIG-106 Chapter 10 Compatibility
- Filter Based on RT Address, T/R bit, Sub-Address
- Advanced Bit Level Error Detection to Isolate Bus Failures
• Advanced Data Handler (ADH)
- For BC, RT, and Multi-RT modes, Option to Combine Control/Status and
Data Structures into Consolidated Structures for each Message.
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