DDC Total-AceXtreme MIL-STD-1553 - Page 30

MIL- STD- 1553 MODES AND ARCHITECTURE
Data Device Corporation DS-BU-67301B-G
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Following the issuance of ADH interrupts, the host can then transfer data from its
ADH memory to designated areas in host space or PCI space memory. These
transfers may be performed over either the parallel CPU or PCI Target interfaces, or
by means of the Total-AceXtreme’s DMA engine and PCI Initiator interface.