DDC Total-AceXtreme MIL-STD-1553 - Page 40

HOST INTERFACE
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nDATA_STRB must be asserted for exactly one host clock cycle for single-word
accesses, and to initiate sequential Synchronous burst transfers. For random
Synchronous burst write transfers, nDATA_STRB must be asserted low through
the entire time of the transfer.
• RD_nWR:
This signal selects between read and write transfers. In 32-bit mode with
POL_SEL = ‘1’, RD_nWR = ‘0’ to read and ‘1’ to write. For all other parallel CPU
interface configurations, RD_nWR = ‘1’ to read and ‘0’ to write.
• ADDR_LAT:
In the Multiplexed mode for the address and data buses (ADMULTI = ‘1’), the
Total-AceXtreme® will latch the host address from CPU_DATA(15:0), along with
MEM_nREG, and (in 16-bit mode only) MSW_nLSW during a positive pulse on
the ADDR_LAT input. For Asynchronous mode, ADDR_LAT must be at least 40
ns wide. For Synchronous mode, ADDR_LAT must meet the setup and hold
times relative to HOST_CLK. In 16-bit multiplexed mode, ADDR_LAT must pulse
high to latch in the address, MEM_nREG, and MSW_nLSW for both the first and
second 16-bit word transfers. In the non-Multiplexed mode for the address and
data buses (ADMULTI = ‘0’), ADDR_LAT must be connected to logic ‘1’.
• CPU_nLAST:
This input signal is used for Synchronous mode only. For single-word
Synchronous transfers, CPU_nLAST must be asserted low through the full
transfer cycle. For Synchronous burst transfers, CPU_nLAST must be asserted
high until the last 32-bit or 16-bit word is written or read over the CPU data bus.
During this last word transfer, CPU_nLAST must be asserted low. CPU_nLAST
is not used in the Asynchronous CPU mode and may be left unconnected.
• MSW_nLSW:
For 16-bit mode, MSW_nLSW is the LSB of the CPU address bus and is used to
select between the upper (bits 31:16) and lower (bits 15:0) 16-bit words. The
polarity of MSW_nLSW is determined by the value of the POL_SEL static input.
In the multiplexed address/data modes, the value of MSW_nLSW is latched
when the ADDR_LAT input is asserted high. In 32-bit mode, MSW_nLSW is not
used and be left unconnected.
• CPU_WORD_EN(1:0):
These two signals should be active throughout the entire transfer cycle, and
operate as follows: