DDC Total-AceXtreme MIL-STD-1553 - Page 71

HOST INTERFACE
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Table 11. Synchronous Timing Parameters
REF DESCRIPTION NOTES
Timing Characteristics
UNITS
MIN TYP MAX
t
DS
CPU_DATA valid setup time (NOTE) 4 ns
t
DH
CPU_DATA valid hold time (NOTE) 0 ns
t
ALS
ADDR_LAT setup time (NOTE) 4 ns
t
ALH
ADDR_LAT hold time (NOTE) 0
t
STPD
CPU_nSTOP delay (Only applicable during Register
Read operation. Low otherwise) (NOTE)
10pF load 2 6.8 ns
t
LS
CPU_nLAST setup time (NOTE) 4 ns
t
LH
CPU_nLAST hold time (NOTE) 0 ns
t
SHC
nSELECT hold cycle time (NOTE) t
CLK
ns
Note: Indicated times are relative to the rising edge of HOST_CLK.
For the 32-bit Synchronous timing diagrams, POL_SEL is assumed to be connected
to logic ‘0’. That is, RD_nWR = ‘1’ to read and ‘0’ to write.
For the 16-bit Synchronous timing diagrams, POL_SEL is assumed to be connected
to logic ‘0’. For these diagrams, the data indicated as “Data A” is bits 15:0, and is
always transferred prior to the data indicated as “Data B”, which is bits 31:16. For the
16-bit Synchronous timing diagrams, RD_nWR = ‘1’ to read and ‘0’ to write.