DDC Total-AceXtreme MIL-STD-1553 - Page 8

LIST OF FIGURES
Data Device Corporation DS-BU-67301B-G
www.ddc-web.com
1/14
vi
Figure 38. Synchronous, Non-Multiplexed Address - 32-bit Sequential Burst Write Transfer
Timing ................................................................................................................................ 78
Figure 39. Synchronous, Non-Multiplexed Address 32-bit - Random Burst Write Transfer
Timing ................................................................................................................................ 79
Figure 40. Synchronous, Non-Multiplexed Address - 16-bit Sequential Burst Memory Read
Transfer Timing ................................................................................................................. 80
Figure 41. Synchronous, Non-Multiplexed Address - 16-bit Sequential Burst Write Transfer
Timing ................................................................................................................................ 81
Figure 42. Synchronous, Non-Multiplexed Address - 16-bit Random Burst Write Transfer
Timing ................................................................................................................................ 82
Figure 43. Synchronous, Multiplexed Address - 32-bit Sequential Burst Memory Read
Transfer Timing ................................................................................................................. 83
Figure 44. Synchronous, Multiplexed Address - 32-bit Sequential Burst Write Transfer Timing
.......................................................................................................................................... 84
Figure 45. Synchronous, Multiplexed Address - 16-bit Sequential Burst Memory Read
Transfer Timing ................................................................................................................. 85
Figure 46. Synchronous, Multiplexed Address - 16-bit Sequential Burst Write Transfer Timing
.......................................................................................................................................... 86
Figure 47. Timing for Assertion of CPU_nSTOP - Output During Synchronous Burst Write
Transfer ............................................................................................................................. 87
Figure 48. Interface Between Host PCI Bus and Total-AceXtreme® - PCI Signal List ............ 90
Figure 49. PCI Parametric Timing ........................................................................................... 93
Figure 50. PCI Slave Burst Write ............................................................................................. 93
Figure 51. PCI Slave Burst Read - PCI Initiator Timing ........................................................... 94
Figure 52. PCI DMA Start Delay .............................................................................................. 95
Figure 53. PCI DMA Burst Write .............................................................................................. 95
Figure 54. PCI DMA Burst Read .............................................................................................. 96
Figure 55. Recommended +1.8V_PLL Filter Network ............................................................. 97
Figure 56. Power-Up Initialization Sequence Timing ............................................................... 99
Figure 57. Total-AceXtreme® Internal Transceiver and Isolation Transformer Connection to
MIL-STD-1553 Bus .......................................................................................................... 100
Figure 58. Mandatory Connections for Integrated Transceivers Connection to External
Transceivers .................................................................................................................... 101
Figure 59. Total-AceXtreme Interface to External McAir Transceiver .................................... 102
Figure 60. Total-AceXtreme® Interface to Fiber Optic Transceivers ..................................... 103
Figure 61. Total-AceXtreme® Pin Diagram ........................................................................... 128
Figure 62. Total-AceXtreme® Mechanical Outline Drawing .................................................. 129