Eaton EDR 3000 - Page 755

EDR-3000 IM02602003E
Name Description
Logic.LE74.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE74.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE74.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE74.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE74.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE74.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE75.Gate Out Signal: Output of the logic gate
Logic.LE75.Timer Out Signal: Timer Output
Logic.LE75.Out Signal: Latched Output (Q)
Logic.LE75.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE75.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE75.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE75.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE75.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE75.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE76.Gate Out Signal: Output of the logic gate
Logic.LE76.Timer Out Signal: Timer Output
Logic.LE76.Out Signal: Latched Output (Q)
Logic.LE76.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE76.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE76.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE76.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE76.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE76.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE77.Gate Out Signal: Output of the logic gate
Logic.LE77.Timer Out Signal: Timer Output
Logic.LE77.Out Signal: Latched Output (Q)
Logic.LE77.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE77.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE77.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE77.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE77.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE77.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE78.Gate Out Signal: Output of the logic gate
Logic.LE78.Timer Out Signal: Timer Output
Logic.LE78.Out Signal: Latched Output (Q)
Logic.LE78.Out inverted Signal: Negated Latched Output (Q NOT)
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