Edge-Core AS7326-56X - Page 157

EDGECORE NETWORKS CORPORATION 2018
157
1
Port51_LED4_G
(P51_Lane3_LED_G)
R/W
1
1: Port51_LED4_G LED OFF (Default)
0: Port51_LED4_G LED ON
0
Port51_LED4_R
(P51_Lane3_LED_R)
R/W
1
1: Port51_LED4_R LED OFF (Default)
0: Port51_LED4_R LED ON
5.12.6.25. Offset 0x3C QSFP28 RGB LED -13 (Read& Write)
Bit
Name
R/W
Reset Value
Description
7:6
Reserve
NA
NA
5
Port52_LED1_Active_B
(P52_Lane0_LED_B)
R/W
0
1: Port52_LED1_B Active ON
0: Port52_LED1_B Active OFF (Default)
4
Port52_LED1_Active_G
(P52_Lane0_LED_G)
R/W
0
1: Port52_LED1_G Active ON
0: Port52_LED1_G Active OFF (Default)
3
Port52_LED1_Active_R
(P52_Lane0_LED_R)
R/W
0
1: Port52_LED1_R Active ON
0: Port52_LED1_R Active OFF (Default)
2
Port52_LED1_B
(P52_Lane0_LED_B)
R/W
1
1: Port52_LED1_B LED OFF (Default)
0: Port52_LED1_B LED ON
1
Port52_LED1_G
(P52_Lane0_LED_G)
R/W
1
1: Port52_LED1_G LED OFF (Default)
0: Port52_LED1_G LED ON
0
Port52_LED1_R
(P52_Lane0_LED_R)
R/W
1
1: Port52_LED1_R LED OFF (Default)
0: Port52_LED1_R LED ON
5.12.6.26. Offset 0x3D QSFP28 RGB LED -14 (Read& Write)
Bit
Name
R/W
Reset Value
Description
7:6
Reserve
NA
NA
5
Port52_LED2_Active_B
(P52_Lane1_LED_B)
R/W
0
1: Port52_LED2_B Active ON
0: Port52_LED2_B Active OFF (Default)
4
Port52_LED2_Active_G
(P52_Lane1_LED_G)
R/W
0
1: Port52_LED2_G Active ON
0: Port52_LED2_G Active OFF (Default)
3
Port52_LED2_Active_R
(P52_Lane1_LED_R)
R/W
0
1: Port52_LED2_R Active ON
0: Port52_LED2_R Active OFF (Default)
2
Port52_LED2_B
(P52_Lane1_LED_B)
R/W
1
1: Port52_LED2_B LED OFF (Default)
0: Port52_LED2_B LED ON
1
Port52_LED2_G
(P52_Lane1_LED_G)
R/W
1
1: Port52_LED2_G LED OFF (Default)
0: Port52_LED2_G LED ON
0
Port52_LED2_R
(P52_Lane1_LED_R)
R/W
1
1: Port52_LED2_R LED OFF (Default)
0: Port52_LED2_R LED ON
5.12.6.27. Offset 0x3E QSFP28 RGB LED -15 (Read& Write)
Bit
Name
R/W
Reset Value
Description
7:6
Reserve
NA
NA