Edge-Core AS7326-56X - Page 97

EDGECORE NETWORKS CORPORATION 2018
97
7
Reserve
NA
NA
6
INTB*IDT8V89307
(IDT8V89307_INT_REQ)
R
1
1: No interrupt
0: There is INTR from IDT8V89307
5
INTB*FAN
(FAN_INT_L)
R
1
1: No interrupt
0: There is INTR from FAN
4
INTB*CPLD3
(CPLD3_INT)
R
1
1: No interrupt
0: There is INTR from CPLD2
3
INTB*CPLD2
(CPLD2_INT)
R
1
1: No interrupt
0: There is INTR from CPLD3
2
INTB* LM75_3
(LM75BD2_INT)
R
1
1:No interrupt
0: There is INTR from LM75_3
1
INTB* LM75_2
(LM75BD1_INT)
R
1
1:No interrupt
0: There is INTR from LM75_2
0
INTB* LM75_1
(LM75BD0_INT)
R
1
1:No interrupt
0: There is INTR from LM75_1
5.12.2.13. Offset 0x0C Interrupt Status-3 (Read Only)
Bit
Name
R/W
Reset Value
Description
7:3
Reserve
NA
NA
2
MAC_INT
(MAC_INT_L)
NA
NA
Reserve
1
MGMT_INT
(INT_MGMT_PHY_N)
R
1
1: No interrupt
0: There is INTR from MGMT PHY
0
PCIE_INT
(PCIE_INTR_L)
R
1
1:No interrupt
0: There is INTR from MAC’s PCIe
5.12.2.14. Offset 0x0D Interrupt Status-4 (Read& Write)
Bit
Name
R/W
Reset Value
Description
7
MASK* P56 QSFP28
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
6
MASK* P55 QSFP28
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
5
MASK* P54 QSFP28
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
4
MASK* P53 QSFP28
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)