Edge-Core AS7326-56X - Page 98

EDGECORE NETWORKS CORPORATION 2018
98
3
MASK* P52 QSFP28
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
2
MASK* P51 QSFP28
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
1
MASK* P50 QSFP28
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
0
MASK* P49 QSFP28
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
5.12.2.15. Offset 0x0E Interrupt Status-5 (Read& Write)
Bit
Name
R/W
Reset Value
Description
7
Reserve
NA
NA
6
MASK*IDT8V89307
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
5
MASK*FAN
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
4
MASK*CPLD3
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
3
MASK*CPLD2
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
2
MASK* LM75_3
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
1
MASK* LM75_2
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
0
MASK* LM75_1
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
5.12.2.16. Offset 0x0F Interrupt Status-6 (Read& Write)
Bit
Name
R/W
Reset Value
Description
7:2
Reserve
NA
NA
1
MASK* MGMT_INT
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
0
MASK* PCIE_INT
R/W
0
1: CPLD blocks incoming the interrupt
0: CPLD passes the interrupt to CPU (Default)
5.12.2.17. Offset 0x10 Module Present-1 (Read Only)
Bit
Name
R/W
Reset Value
Description