Table 19 SAS Disk Drive LEDs
SAS Disk Drive StateStatus LEDActivity LED
Offline or not configuredOffOff
Normal operation; no disk activityOffSolid green
Normal operation; disk read or write activityOffFlickering green
Offline, no disk activity; predictive failureFlashing amber - 1/secOff
Online, no disk activity; predictive failureFlashing amber - 1/secSolid green
Disk activity; predictive failureFlashing amber - 1/secFlickering green
Offline; no disk activity; critical faultSolid amberOff
Offline; drive selected by locator functionSolid blueOff
Drive rebuildingOffFlashing green - 1/sec
LAN LEDs
There are four LAN LEDs on the front panel of the server blade. They are NIC 1 through NIC 4.
Table 20 details the functions of the LAN LEDs.
Table 20 1 GB LAN States
StateLED Color
No linkOff
Link foundSteady Green
LAN activity on network linkFlashing Green
Boot Process LEDs
Table 21 shows the normal boot process, as reflected in changes to front panel LED states:
Table 21 Normal Boot Process LED States
Normal Power-Up Through HP-UX BootPowerHealthStep
No AC power to the server blade.OffOff1
Server blade is shut down (server is off), AC power and
standby power is active, last health status was healthy.
AmberOff2
Server blade power rails are on when Power switch is
toggled. Hardware drives power LED.
Steady GreenOff3
Server blade has powered up and is either at EFI, booting,
or at OS.
Steady greenSteady green4
The following list itemizes the steps that characterize basic platform boot flow:
1. Server blade power switch requests power from the Management Module (the microcontroller
that manages the enclosure power and cooling). Once the power is request is granted, server
blade power turns on. After the power sequence has completed successfully, BMC releases
system reset.
2. Initial processor firmware code fetch is Platform Abstraction Layer (PAL) code from FEPROM
in processor-dependent hardware (PDH), retrieved 4 bytes at a time by the data
multiplexer/demultiplexer controller (DMDC) in zx1. No shared memory or I/O devices are
available at this time. They are not initially configured.
3. Firmware code stack is initially in battery-backed RAM (BBRAM) in PDH, retrieved 4 byes at
a time, through the PDH and DMD buses.
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