HP MR Gen10 Plus - Cache Error Checking and Correction (ECC)

Cache Error Checking and Correction (ECC)Cache Error Checking and Correction (ECC)
Error checking and correction (ECC) DRAM technology protects the data while it is in cache. The ECC scheme generates 8 bits of check
data for every 64 bits of regular data transferred. The memory controller uses this information to detect and correct data errors
originating inside the DRAM chip or across the memory bus.
Cache Error Checking and Correction (ECC) 74